1. Field of the Invention
The present invention relates to a method of manufacturing a multilayer wiring board in which a plurality of insulating layers and a plurality of conductor layers are alternately laminated.
2. Description of Related Art
In the related art, a method is known in which, after a semiconductor chip is mounted on an insulating layer, an insulating layer is further formed so as to cover the semiconductor chip, thereby manufacturing a multilayer wiring board embedded with a semiconductor chip (for example, JP-A-2006-339421).
However, in the technique described in JP-A-2006-339421, when forming the insulating layer so as to cover the semiconductor chip, the pressing force of the insulating layer formed on the semiconductor chip against the semiconductor chip is applied to the semiconductor chip, causing an increase in a failure rate of the semiconductor chip embedded in the multilayer wiring board.